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Monterey Design Systems Adds New Functionality Creating Unparallelled Top-Down Hierarchical Solution
SUNNYVALE, Calif.--(BUSINESS WIRE)--Oct. 8, 2001--Monterey Design
Systems® today announced version 2.2 of IC Wizard, the hierarchical
design planner that drives Monterey's System-Driven Physical
Design(TM) solution. With this release, Monterey is the first to
provide the full spectrum of capabilities needed to restructure and
optimize physical hierarchy. Monterey is also the first to provide a
hierarchical global router and port placer that take advantage of
visibility through all levels of hierarchy.
``IC Wizard offers the most comprehensive set of hierarchy
management functionality today bar none,'' said Mike Barone, product
marketing director at Monterey. ``With release 2.2 we are giving our
customers hierarchical capabilities that have not been available
commercially until now. Previous releases of the product have already
been production proven by several leading semiconductor companies.
STMicroelectronics was the first to tape out a chip using IC Wizard in
September 2000.''
Hierarchical Design is More than Just Placing Ports
``When you examine the EDA landscape, you see a number of companies
trying to solve yesterday's gate-level problems. This is because many
attempts at building a hierarchical solution have started at the
gate-level and worked up from there. This approach limits those tools
to low-level capabilities such as partitioning gate-level netlists and
placing ports,'' Barone continued. ``To design complex chips containing
tens of millions of gates requires the ability to operate at higher
levels of physical abstraction working with functional blocks rather
than individual gates.''
A hierarchical physical design flow must start early in the design
cycle, pre-RTL, and continue in lock step with the logic design and
physical design all the way through final tape out. This top-down
hierarchical flow starts with the initial partitioning of the design
into sub-systems. Chip-level constraints must be partitioned and
allocated to the individual sub-systems. Each sub-system may then be
compartmentalized and off-loaded to separate processes for logic
synthesis, logic optimization, physical prototyping, and final
implementation. During this process, the chip designers must develop a
physical hierarchical structure that will meet all constraints and not
exceed the capabilities of the physical design tools. When complete,
the sub-systems are re-assembled at the top level to complete the
design. The hierarchical design planner is responsible for the initial
partitioning into sub-systems, the allocation of the constraints to
the sub-systems, the management and optimization of the hierarchical
structure, and the communication between processes throughout the
entire flow.
New Features in IC Wizard Version 2.2
New functionality added to IC Wizard 2.2 includes:
- Hierarchical global routing and port placement -- A global
router that has limited visibility of the hierarchical
structure will not be able to find the best routes between
components embedded within hierarchical structures. IC
Wizard's global router has full visibility through multiple
levels of hierarchy. This results in an optimal route and also
allows it to find the best position and layer assignments for
the ports.
- Re-structuring -- When dealing with high-performance designs,
the user may wish to physically re-locate a logic module from
one part of the hierarchy to a completely separate part. Older
generation hierarchy managers might allow the user to move a
logic module up or down the structure, but they would not
allow you to re-locate it to a completely different branch of
the tree. IC Wizard gives the user full flexibility to
re-configure the hierarchical tree structure for optimal
physical implementation. IC Wizard also allows the user to
automatically bubble-up all hard blocks, or only selected hard
blocks to the top-level.
- Constraint management -- The design planner must allocate
chip-level constraints to individual blocks that may be used
to drive the design and implementation of each of the blocks.
IC Wizard automatically adjusts the block placement when
necessary and supports constraint allocation and re-allocation
of timing slack as well. It also allows for adjustments to
constraints to accommodate changes made to the physical
hierarchy by operations such as those listed above.
Version 2.2 was built on IC Wizard's original powerful foundation
of proven functionality, which includes capabilities such as:
- Automatic block placement and shaping -- Physical hierarchical
design requires the ability to place and shape blocks. IC
Wizard offers the only production proven block placer
available today.
- Multiple levels of hierarchy -- SOC designs today contain two
or more levels of physical hierarchy. IC Wizard supports an
unlimited number of levels of physical hierarchy.
- Traversal -- In order to manage hierarchy, the user must be
able to quickly and easily traverse the entire hierarchical
structure. IC Wizard uses the ``file manager'' metaphor to allow
users to easily expand and collapse hierarchical structures,
then open and view as many structures simultaneously as
needed.
- Clustering -- In most hierarchical designs, it is desirable to
cluster together logical modules into larger physical
partitions because physical layout tools generally have higher
capacities than synthesis tools. IC Wizard allows the user to
select and cluster multiple objects together, adding levels of
physical hierarchy as needed.
- Flattening -- Once a design has been clustered into physical
partitions and synthesized down to the gate-level, the user
will generally flatten all hierarchy within a physical
partition. IC Wizard allows the user to automatically flatten
down to specified levels, or all the way to the bottom of the
tree.
Pricing and Availability
IC Wizard 2.2 is available immediately on all supported platforms.
Pricing begins at $124,000 per year (U.S. list price).
About Monterey Design Systems
Monterey Design Systems is the only System-Driven Physical Design
solution provider, giving customers the fastest and most advanced
System to GDSII approach for deep sub-micron SoC design. The company
combines superior technology in design planning, physical prototyping
and automated physical implementation to provide a revolutionary
physical design flow that begins at the system level and produces a
manufacturing ready layout. Leading semiconductor companies have
adopted Monterey's innovative products to dramatically increase their
design productivity. Pioneering new business models that align
financial rewards to its customers' success have attracted customers
to the company's patented products. Monterey Design Systems is
privately held and backed by leading venture and industrial investors.
The company partners with leading EDA companies such as Cadence
(NYSE:CDN) and Synopsys (Nasdaq:SNPS - ) to ensure interoperability in
ASIC and COT design flows. Monterey Design Systems is located at 894
Ross Drive, Sunnyvale, CA. 94089-1443, tel: 408/747-7370, fax:
408/747-7377, http://www.montereydesign.com/.
Note to Editors: Monterey and Monterey Design Systems are
registered trademarks and System-Driven Physical Design is a trademark
of Monterey Design Systems. All other trademarks and registered
trademarks are the property of their respective owners.
Contact:
Monterey Design Systems, Sunnyvale
Cedric Iwashina, 408/548-4910
cedric@mondes.com
or
Lee Public Relations
Barbara Marker, 650/363-0142
barbara@leepr.com
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